Solid state sign system



Dec. 22, 1970 E. JQscHuLENBE-RG, SR., ET Al. 3,550,112

I SOLD STATE SIGN SYSTEM D 22, 1970 E. J. SCHULENBERG, SR., ETAL SOLIDSTATE SIGN SYSTEM Original Filed March n,

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' soLID STATE SIGN SYSTEM Original Filed March 2, 1965 9 Sheets-Sheet 51 wmwl o m D 22, 1970 E. J. scHuLENBERG, SR., ET Al- 3550112 l SOLIDSTATE SIGN SYSTEM 9 Sheets-Sheet 4 Original Filed March 2. 1965 S Us@\nmm NQNN vr NN Sv femm NIIIII -illlllll lllll Il EN T.

D- 22, 1970 E. J. scHULENBERG, SR., ET AL 3,550,112

SOLID STATE SIGN SYSTEM Y Original Filed March 2, 1965 9 Sheets-Sheet 5Dec. 22, 1970 E. .1. SCHULENBERG, SR., ETA*- SOLID STATE SIGN SYSTEMOriginal Filed March 2, 1965 9 Sheets-Sheet s Dec. 22, 1970 E. .1.SCHULENBERG, SR., ET AL soLID STATE SIGN sYsTEM Original Filed March 2,'1965 9 Sheets-'Sheet 7 E. J. SCHULENBERG, SR., ET A1. 3,550,112

Dec. 2,2, 1970 SOLID STATE SIGN SYSTEM 4OriginalY Filed March 2, 1965Mal Mm 9 Sheets-Sheet 8 3.529 @www Dec. 22, 1970 E. J. scHuLENBERG, SR,ETAL 3,550,112

SOLID STATE SIGN SYSTEM 9 SheetsvSheet 9 Original Filed March 2. 1965United States Patent 3,550,112 SOLID STATE SIGN SYSTEM Edward J.Schulenberg, Sr., Danville, Ill., and Ervin M. Ball, Indianapolis, Ind.,assignors to Time-O-Matic, Inc., Danville, lll., a corporation ofIllinois Original application Mar. 2, 1965, Ser. No. 436,469. Dividedand this application Sept. 27, 1968, Ser.

Int. Cl. G09f 9/36 U.S. Cl. 340-334 3 Claims ABSTRACT 0F THE DISCLOSUREA running sign lamp bank system wherein the lamps of the bank areenergized to different degrees depending on the ambient light conditionsand the frequency or rate at which a given lamp is energized to providea relatively This application is a division of application Ser. No.436,469, filed Mar. 2, 1965.

The present invention relates to improvements in a running sign system,although some aspects of the invention have a broader application.

Due to the manner in which running signs were heretofore operated, itwas necessary for each alphabet or numerical character and the spacebetween characters to occupy a standard sized block. For example, anarrow letter (like I and T) and the spaces on the opposite sidesthereof occupied the same sign area as a much wider letter and theassociated spaces, iwith the result that the spacing between narrowletters rwas much greater than the spacing `between wider letters.Because of the circuit logic and arrangement of the present invention,each letter or numeral and the spaces on the opposite sides thereofoccupy a sign area proportional to the width of the letter or numeral sothat the spacing between all letters of a word or number can be thesame.

The lamps used in the lamp banks generally require a finite time to warmup, and the intensity of the light generated by a lamp is dependent, inpart, upon the average on time of the lamp. Therefore, in a running signfor a letter like the letter E which requires simultaneous energizationof a number of adjacent lamps in a row to V form the upper and lowerlegs of the letter, the average intensity of the light generated by thelamps which reproduce the upper and lower legs of the letter will lbemuch greater than the lamps which form the vertical leg of the lettersince the latter lamps are energized for only a short period whereaseach lamp forming the upper and lower legs of the letter moving down thelamp bank remains energized for a prolonged period. The resultantsubstantial variation in lamp intensity is undesirable both from anaesthetic and economical viewpoint. Several features of the presentinvention reduce this problem by providing a sign where the differencesin intensity of the lamps forming different parts of any letter arereduced substantially.

The lamps which form the vertical leg of a letter are frequently on forsuch a short period of time that, considering the normal speed at whicha running sign moves, there is barely enough time for the light to warmup to reach an acceptable intensity. Several features of the presentinvention provide a greater intensity for these lamps without reducingthe speed of the running sign.

Another problem which is overcome by the present in- ICC vention is thatthe overall required intensity of a lighted sign varies with the time ofday. One of the features of the invention automatically varies the lampintensity wiih the ambient light conditions.

Other aspects of the invention relate to various details of thecircuitry which result in a minimum power drain, maximum reliability,and minimum circuit complexity.

The various features of the invention are disclosed in the specificationto follow, the claims and the drawings wherein:

FIG. l is a basic block diagram of one form of running sign systemincorporating features of the present invention;

FIG. 1A is a fragmentary view of a portion of the tape fed to theequipment shown in FIG. 1;

FIG. 2 is a detailed block diagram disclosing a basic form of lampcontrol circuit and character memory unit forming part of the signsystem of FIG. 1;

FIG. 2A is a diagrammatic view of the various stages of the shiftregister circuits making up the character memory unit;

FIG. 3 is a detailed block diagram illustrating a preferred lamp controlcircuit;

IFIG. 3A is a detailed block diagram of the A and B shift pulsegenerator circuit forming part of the sign system of FIG. l;

FIG. 4 is a detailed block diagram illustrating a preferred characterread control circuit forming part of the sign system of FIG. 1;

FIG. 5 is a timing dia'gram illustrating the relative phases of variouswaveforms in the circuits of FIGS. 3 and 4; r

FIG. 6 shows the lamps which are energized to produce the character Ewhen the lamp control circuit of FIG. 3 is utilized;

FIG. 7 shows a modified lamp control circuit where alternate lamps areenergized at a given time;

FIG. 7A is a timing diagram illustrating the relative phase of variouswaveforms in the circuit of FIG. 7;

FIG. 8 shows the lamps which are energized to produce the character Efor the lamp control circuit of FIG. 7;

FIG. 9 shows a modified lamp control circuit where successive lamps areenergized at the same time;

FIG. 10 shows an energizing circuit for the lamps of' the lamp bankwhich provides for selective dimming of certain rows of the lamp banksand control over the intensity of the lamps in accordance with theambient light conditions of the lam-p bank;

FIG. 11 shows the waveform of the current flow through the lamps of thelamp bank and the manner in which the average current flow there throughis controlled;

FIG. l2 illustrates a variable phase pulse circuit operated from aphotocell which forms part of the circuit of FIG. 10;

FIG. 13 illustrates a basic modification of the circuit logic of thevarious shift register circuits shown in FIGS. 3 and 4;

FIG. 14 illustrates a block diagram of a combined running and stationarysign system with provision for controlling the average light intensityof the lamp bank in accordance with the ambient light conditions;

FIG. 15 illustrates an exemplary circuit diagram 0f a binary to singleoutput matrix and the character set-up matrix forming a part of thecircuits illustrated in FIGS. 1 and 14; and

FIG. 16 is an exemplary circuit diagram of a portion of the lamp controlcircuit of the embodiment of the -invention shown in FIG. 3 andillustrating the circuitry of the bi-stable circuits which control thegated diodes associated with the lamps in the lamp bank.

GENERAL A.DESCRIPTION Referring now to the basic block diagram of FIG.l, all of the various forms of the invention to be `described are forthe purpose of controlling the energization of rows of lamps in a lampbank 2, seven such rows being illustrated by way of example, andidentified by reference characters 2a, 2b, 2c, 2d, 2e, 2f, and 2g. Thecorresponding lamps in each of the rows are preferably aligned incolumns. The lamp bank 2 is illustrated as being a horizontallyelongated lamp bank capable of receiving relatively long running signs.-(It should be recalled, however, that some aspects of the inventionhave application to stationary sign systems.)

The lamp bank 2 is controlled by a very unique static element logiccontrol circuit including a lamp control circuit 4 which directlycontrols the energization of the various lamps in the bank. The lampcontrol circuit 4 most advantageously comprises a number of individualshift register circuits to be described, one such circuit being providedfor each row of lamps. Lamp energizing markers are sequentially fed intothe stages of the shift register circuits of the lamp control circuitassociated with the group of lamps at the right-hand of the lamp bank 2and in a pattern corresponding with the particular alphabet or numericalcharacter being first displayed on the lamp bank at a given moment. Thevarious pat- Vterns of lamp energizing markers entered -into the shiftregister cir-cuits are sequentially advanced through the various stagesof the shift register circuits. The presence of a lamp energizing markerin a stage of a shift register circuit associated with a particular lampwill result in lthe energization of that lamp.

The lamp energizing markers are fed into the shift register circuits ofthe lamp control circuit 4 from a character memory unit `6. In thepreferred form of the invention, the character memory unit 6 comprises aseries of shift register circuits 6-1, 6-2, 6 3, 6 4, 6-5, 6 6, and 6-7(FIG. 2A), `one such circuit being associated with each row of lamps inthe lamp bank. Each shift register circuit of the lamp control circuithas a number of stages a, bf c, d, e, f (a being the first stage at therighthand end thereof) equal in number to the number of lamps which mustbe energized in a row of lamps for the widest alphabet or numericalcharacter to be displayed on the lamp bank plus a number of stages g andlz equal to the number of lamps which remain de-energized in the -spacebetween successive characters. (It is assumed, for example, that thewidest character to be displayed on the lamp will require energizationof six lamps in a given row of lamps and that the space betweensuccessive characters Iwill occupy two columns of lamps of the lampbank.) A pattern of lamp energizing markers (each identified by an x inFIG. 2A) are first placed within the stages a through f of the variousshift register circuits of the character memory -unit `6 (the f stagecontaining the marker forming `the left-hand portion of the characterinvolved) in a pattern which corresponds to the particular alphabet ornumerical character read by a tape reader 7 to which punched tape 7a(FIG. 1A) is fed. The advancement of lamp energizing markers in anyshift register circuit will be to the left and so as the lamp energizingmarkers shown in FIG. 2A are shifted in the shift register circuit 6-1through 6-7, the outline E of markers shown moves to the left and, aswill be explained in more detail, will be transferred into the righthand stages of the corresponding shift register circuits of rthe lampcontrol circuit 4. The number of shift operations required to empty thecharacter merging unit of markers thus varies with the width of thecharacter involved.

In the exemplary embodiment of the invention being described, it will beassumed that a 6-element binary coded group of punched holes 7a isutilized to indicate each alphabet or numerical character, the codeoccupying a single column extending transversely across the tape 7a. Thetape reader 7 reads one column of binary coded characters at a time. Thetape 7a is automatically advanced in accordance with well establishedtape reader practice each time the tape reader receives an advancesignal on an advance input line 7b. The tape reader 7 has a number ofoutput lines 7c corresponding to the number of binary coded charactersin each code group on the tape 7a so that the voltage or current patternon the output lines 7c duplicates the particular code being read `by thetape reader. The output lines '7c extend to a binary to single outputmatrix 8 which energizes one of a number of output lines collectivelyidentified by reference 8a, the particular output line being energizedcorresponding to the alphabet or numerical character read by the tapereader 7a at a given instant.

The output lines 8a of the binary to single output matrix 8 areconnected to a character set-up matrix 10 and a character width matrix15. The character set-up matrix 10 includes groups of diodes 11 (FIG.l5) associated with each output line of the matrix 8 which extend tothose stages of the various shift register circuits making up thecharacter memory unit 6 which form the pattern of the characterinvolved. Thus, depending upon the particular output line 8a which isenergized, a pattern of lamp energizing markers is set up in the stagesof the character memory unit 6 corresponding to the alphabet ornumerical character being read by the tape reader 7.

The shift register circuits of the lamp control circuit 4 and thecharacter memory unit 6 associated with a given row of lamps in the lampbank are connected in tandem so that the lamp energizing markers aretransferred one column of markers at a time from the left hand stages lzof the various shift register circuits of the character memory unit 6 tothe right hand stages of the shift register circuits of the lamp controlcircuit 4. The advancement of the lamp energizing markers in thecircuits 4 and 6 are under control of output pulses from a shift pulsegenerator 13 of any well-known type which feeds shift pulses to shiftinput terminals 4a and 6a of the lamp control and character memory unitcircuits 4 and 6.

When all of the lamp energizing markers have been fed from the charactermemory unit 6, this condition is sensed in any one of a number of ways,as by the provision of a character read control unit 14 which etfectsthe feeding of an advance pulse to the advance input terminal 7b of thetape reader 7 so that the next column 7a of binary coded information onthe tape 7a is fed to the tape reading position of the tape reader 7.When this occurs, a new pattern of lamp energizing markers are enteredinto the character memory unit 6.

The character read control unit 14 may take a variety of forms; In thepreferred form of the invention, the character read control unitcomprises a single shift register circuit having the same number ofstages as any one of shift register circuits of the character memoryunit 6. A character width matrix 15 is provided which may be a diodematrix which has a separate output 15a for each different characterwidth. For example, if the widest character occupies six lamps on thelamp bank, the character width matrix 15 will have six output linesrepresenting the six possible character widths. The character widthmatrix 15 is coupled to the output lines 8a to energize the output 15awhich identifies the width of the particular character being read by thetape reader 7. A marker will be placed in the stage of the shiftregister circuit making up the character read control unit 14 whichcorresponds to the right-hand-most .stage of the shift register circuitsof the character memory unit 6 which contains a lamp energizing marker.

The output of the shift pulse generator 13 is fed to a shift inputterminal 14a of the character read control unit 14 so that the marker inthe shift register circuit making up the character read control unit 14will advance in synchronism with the advancement of the lamp energizingmarkers in the character memory unit 6. As the marker leaves theleft-hand-rnost stage of the shift register circuit of the characterread control 14, a signal is fed on a character shift line 17 to theadvance input terminal 7b of the tape reader 7, bringing the next binarycode group into reading position as above explained.

As previously indicated the provision of the character memory unit `6 asdescribed above will effect a fixed spacing between all characters in aword or number group independently of the width of the character. Thisis a substantial improvement over the appearance of the usual runningsign wherein the spaces between successive characters vary with theWidth of the character due to the fact that a given size character blockis utilized for all characters displayed on the sign.

LAMP CONTROL AND CHARACTER MEMORY CIRCUITS OF FIG. 2

FIG. 2 illustrates a generalized form for the lamp control circuit 4when using gated diodes for controlling the energization of the variouslamps, the gated diodes being identified by reference 20 followed by analphabet character indentifying the row of lamps involved and a numberidentifying the column of lamps involved. In the circuit illustrated,the anode electrode of each gated diode is connected to one of the lampsof the lamp bank, the lamps being identified by reference number 22followed by an alphabet character identifying the row of lamps and anumber identifying the column of lamps involved. the lamps, in turn, areconnected to a common power bus 24 leading to the output of a full-waverectifier circuit 26 which would normally be fed from a cornmercialsource of 60 cycle alternating current.

The cathode electrodes of the gated diodes 20 are grounded and thecontrol electrodes thereof are connected respectively to lamp controlbistable or fiipeop circuits identified by reference 28 and an alphabetcharacter identifying the associated row of lamps and a nurnberidentifying the associated column of lamps involved. When one of thebistable circuits 28 is triggered into a set state, a direct current(DC) voltage is fed to the control terminal of the associated gateddiode 20` to effect the firing thereof. The gated diode continues in ahighly conductive state for the remainder of the half cycle of therectified current pulsation which flows through the gated diode and thelamp associated therewith independently of the voltage in the controlelectrode thereof. The control electrode gains control over theconductive state of the gated diode when the current drops to near zero,that is below what is referred to as a holding current level. The gateddiode will again fire at the beginning of the next half cycle if theassociated bistable circuit remains in the set state.

Each of the bistable circuits 28 forms part of a stage of a shiftregister circuit with the other bistable circuits associated with thelamps of the same row of lamps of the lamp bank 2. Although anyconventional shift register circuit may be utilized in the practice ofthe broad aspects of the present invention, certain aspects of thepresent invention deal with the nature of the shift register circuitwhich has particular advantages in a lamp control circuit of the typenow being described.

The bistable circuits 28a-2, 28a-3, etc., other than the right-handmostbistable circuit 28a-1, etc., of each shift register circuit of the lampcontrol circuit 4 is controlled by a condition sensing means generallyindicated by reference number 30 followed by an alphabet characteridentifying the associated row of lamps and a number identifying theassociated column of lamps. The first bistable circuit 28a-1, etc., ofeach shift register circuit is set by a signal fed to a set inputterminal S thereof from the last stage of the corresponding shiftregister circuit of the character memory unit 6. (The aforementionedlamp energizing marker is represented by a set state of a bistablecircuit 28.) The condition sensing means 30 associated with eachbistable circuit determines Whether the associated bistable circuit willbe set or maintained in the reset state. A number of different circuitsfor the condition sensing means 30 will be described. Sufiice it to sayat this point in the specification, each condition sensing means 30effects the setting of the associated bistable circuit 28 at a point intime coincident with the presence of an advance pulse on an advancesignal line 33 if the bistable circuit 28 to the right of it is in a setstate prior to the generation of the advance pulse. If, on the otherhand, the latter bistable circuit is in a reset state, the conditionsensing means 30 involved will either maintain or effect a resetting ofthe bistable circuit which it controls on the presence of the nextadvance pulse on the advance signal line 33.

The shift register circuits of the character memory unit 6 are, in mostrespects, similar to the shift register circuits just described inconnection with the lamp control circuit 4, and, accordingly, except forthe first stage of each of the shift register circuits of the charactermemory unit 6, includes a bistable circuit identified by reference 35followed by an alphabet character identifying the associated row oflamps and a number identifying the associated column of lamps. Eachshift register circuit stage except the first one includes a conditionsensing means identified by reference number 37 followed by an alphabetcharacter and a number respectively utilized to identify the associatedrow and column of lamps. The first stage of each shift register circuit6-1, or 6-2, or 6 3, etc. of the character memory unit comprises abistable circuit 35u-1, or 35b-1, etc. As previously indicated, each ofthe shift register circuits of the character memory unit 6 has eightstages in the exemplary embodiment of the invention, only five 0f whichappear in FIG. 2. The shift register circuits associated with thecharacter memory unit 6 are different from those of the lamp controlcircuit 4 in that the former are initially set in accordance with agiven pattern corresponding to the associated alphabet character ornumber by set input lines identified by reference number 40 followed byan alphabet character and number identifying the associated row andcolumn of lamps. The various set lines 40 are the previously mentionedoutput lines 10a of the character set-up matrix 10 described inconnection with FIG. l.

Once the various bistable circuits 35 are set, the subsequent presenceof advance pulses on the advance signal line 33 will result in thesequential movement of the pattern of set states involved toward theleft-hand end of each of the shift register circuits making up thecharacter memory unit 6. As previously indicated, the set state of alast stage of the bistable circuits making up the character memory unit6 will result in the setting of the first bistable circuit of the firststage of the associated shift register circuit of the lamp controlcircuit 4 upon the occurrence of the next advance pulse on the advancesignal line 33.

SPECIFIC LAMP CONTROL CIRCUIT OF FIG.3

Refer now to FIG. 3 which illustrates a specific lamp control circuit 4wherein the condition sensing means 30 are bistable circuits (to bereferred to as intermediate bistable control circuits) like the lampcontrol bistable circuits 28.

Each of the bistable circuits 28 and 30 has a set input terminal S and areset terminal R for respectively setting and resetting the bistablecircuit when signals of proper polarity (to be referred to as set andreset signals) are fed thereto. The reset terminals of the lamp controlbistable circuits 28 are connected by conductors 42 to an A signal bus33 upon which pulses appear having the phase indicated by the Waveform(b) shown in FIG. 5. It should be noted that these A pulses occur duringalternate half cycles and a short time after the beginning of each halfcycle of the A.C. rectified current fed to the lamps 22 from the outputof the rectifier circuit 26. The reset terminals of the intermediatebistable circuits 30 are connected to a B signal bus 33 on which pulsesappear having the phase indicated by the 4waveform (c) shown in FIG. 5.The B pulses occur during the same half cycles as the A pulses and aredelayed by a small angle from the A pulses.

Each of the lamp control bistable circuits 28 has an output line 41 andeach of the intermediate bistable circuits has an output line 41. Itwill be assumed that each of these output lines will have appliedthereto a negative or ground voltage when the bistable circuit is in areset state and a positive voltage when the bistable circuit is in a setstate, The output line 41 is connected to the control electrode of theassociated gated diode to fire the same when the bistable circuit is ina set state. The gated diode will continue in a conductive stateindependently of the voltage thereafter fed to the control electrodethereof for the remainder of the half cycle of current flow involved.Near the end of the half cycle, the current flowing through the gateddiode will drop below what is referred to as a holding current level,wherein the control electrode thereof regains control. The gate diodewill continue to conduct in subsequent half cycles until the associatedbistable circuit 28 is reset.

As is apparent from waveform (b) in FIG. 5, each lamp control bistablecircuit 28 which is in a set state will be reset every other half cycleon the occurrence of an A pulse. (As previously indicated, the settingof a bistable circuit 28 will have no effect on the control of theassociated gated diode until the end of the half cycle of current flowsthrough the gated diode involved.) Since the A pulses occur duringalternate half cycles, once a gated diode has become conductive it vwillremain conductive to energize the associated lamp for the remainder ofthe half cycle involved and for an added two full half cycles, which,when the source of energizing voltage for the lamps in a full waverectified 60 cycle voltage source, provides an adequate warm-up time fora bright running sign display.

As previously indicated, the interconnections between the variousbistable circuits 28 and 30 form a shift register circuit. To this end,a capacitor 55 is connected between the output line 41 of each of thelamp control bistable circuits 28 and the set terminals of theintermediate bistable circuit 30 of the next stage of the shift registercircuit. The intermediate bistable circuits 30 are designed so that onlya negative going pulse fed to the set terminals S thereof will effectthe setting thereof. Such a negative going voltage occurs when a givenlamp control bistable circuit ZS is switched from a set to a reset stateby the feeding of an A pulse to the reset input R thereof.

The shift register circuit operates in such a manner that when a givenlamp control bistable circuit 28 is in a set state, this set state willbe transferred to the next stage of the bistable circuit when advancepulses are fed to the shift register circuit. The A and B pulses, in themanner now to be explained, act as shift or advance pulses for the shiftregister circuit. Assuming that the first lamp control bistable circuit28a-I is in a set state, upon the occurrence of the next A pulse on theline 33', the bistable circuit is reset which generates a negative goingvoltage on the output line 41 which is coupled through the capacitor tothe next intermediate bistable circuit 30a-2 to set the same. If thebistable circuit 28a-1 was in a reset state during the occurrence of theA pulse, the state of the bistable circuit will not change and no signalvoltage will be coupled through the capacitor 55, and the intermediatebistable circuit 30a-2 will remain in its reset state. In effect, theintermediate bistable circuits act as memory units which memorize thelast state of the preceding lamp control bistable circuit following thegeneration of each A pulse.

In the case where the intermediate bistable circuit 30a-2 is triggeredto a set state, the bistable circuit will immediately thereafter bereset upon the generation of the next B pulse coupled to the resetterminal R thereof. When the intermediate bistable circuit like 30a-2 isreset, a negative going voltage will appear on the output line 41thereof which is coupled by a capacitor 57 to the set input terminal ofthe lamp control bistable circuit 28a-2. If the intermediate bistablecircuit 30a-2 had not been previously set, no signal will appear at theoutput line 41 or at the set input terminal S of the lamp controlbistable circuit 28a-2 upon the occurrence of the B pulse. It is thusapparent that the arrangement of bistable circuits shown in FIG. 3constitute a shift register circuit wherein a vgiven pattern of set andreset states proceeds down the various sages of the shift registercircuit at a rate depending upon the rate of the A and B pulses.

Each gated diode 20 has a control terminal connected to an output line41 of a lamp control bistable circuit 28 and as a lamp control bistablecircuit is triggered to a set state the associated gated diode will befired into a conductive state. As previously indicated each such gateddiode will continue to conduct for a full half cycle once it has beenfired independently of the voltage on the control terminal thereofduring which interval the associated lamp 22 will be energized. Thegated diode will be re-red at the beginning of the next two half cyclesbecause the next A and B pulses will not recur until after the beginningof the last of the latter half cycles. Each lamp will thus be energizedfor about three half cycles, giving adequate warm-up time despite thefact that the A and B pulses are spaced only two half cycles (in a 60cycle per second timing source). As one lamp becomes energized, theprevious energized lamp remains energized until the end of the halfcycle involved. This overlapping of the energization of successive lampsof the lamp bank allows the lamps to reach and remain at high intensityfor a sufficient period to provide a proper average intensity of thesign despite the high pulse rate.

A AND B SHIFT PULSE GENERATOR 13 OF FIG. 3A

In the preferred form of the invention, the A and B pulses are generatedin a manner like that shown in FIG. 3A. To this end, a source ofcommercial 60 cycle voltage is fed to a full wave rectifier circuit 60which provides at the output thereof a full Wave rectified waveform (a)such as shown in FIG. 5. (The rectifier circuit 60 may be the samerectier used to produce the energizing voltage waveform applied to thebus 24 extending to the lamps 22 of the lamp bank.) The full waverectitied voltage is fed to the input of a suitable clipper circuit 62which produces a waveform W2 like that shown at the output of theclipper circuit 62 in FIG. 3A. This waveform is fed to a conventionaldifferentiating circuit `64 which produces positive and negative goingpulses P1 centered about the sloping sides of the waveform W2. Thesepulses are fed through a rectier 66 which removes pulses of one polarityto leave pulses of opposite polarity having a rate of 120 pulses persecond. These pulses are fed directly to (or indirectly through anamplifier) to a divider circuit 68 which may have a manual control knob70 providing for a selection of different division factors to produce 'aselection of pulse rates -for the A and B pulses which varies the speedof the running sign. The pulse rate illustrated in FIG. 5 is a 60 cyclesper second rate which represents a divide by 2 operation of the dividercircuit. By adjusting the manual control 70 to produce a division by 4 apulse rate of 30 cycles per second is produced which produces a rate ofadvance of the running sign which is one-half that produced by a 60cycle A and B pulse rate.

The output of the divider circuit 68 is split into two branches, one ofwhich extends to an A terminal, representing the source of A pulses andthe other of which extends through a suitable delay means 72 whichproduces a slight delay in the pulses, fed to a B terminal representingthe source of B pulses.

9 CHARACTER READ CONTROL CIRCUIT 14 OF FIG. 4

As previously indicated, the character memory unit 6 and the characterread control circuit 14 comprises one or more shift register circuits.These shift register circuits are preferably similar to the shiftregister circuit just described in connection with FIG. 3 which controlsone of the rows of lamps of the lamp bank. The character read controlcircuit 14 comprises a series of bistable circuits forming the variousstages of a shift register circuit as illustrated in FIG. 4, the stagesbeing respectfully identified by reference numerals 14-1, 14-2, 14-3,through 14-8. Except for the first stage of the shift register circuitillustrated, which comprises only a single bistable circuit 77, eachstage of the shift register circuit includes an intermediate or memorybistable circuit 74 having a set input terminal S coupled through acapacitor 75 to the output 76 of the bistable circuit 77 of thepreceding stage. Each bistable circuit 77 of the second and subsequentstages of the shift register circuit has a set terminal S coupledthrough a capacitor 79 to the output of the associated intermediate ormemory bistable circuit 74. Each of the memory bistable circuits 74 hasa reset terminal R connected to the B signal bus 33 and each of thebistable circuits 77 has a reset terminal R connected to the A SignalBus 33.

Unlike the shift register circuits forming part of the lamp controlcircuit 4, the shift register circuit making up the character readcontrol circuit 14 has individual set lines 80-1, 80-2, 80-3, 80-4,80-5, and 80-6, extending directly to the set terminals S of thebistable circuits 77 so as to preset simultaneously all of the stages toa given state of operation. The set lines 80-1, 80-2, etc. represent theoutput lines of the character width matrix 1S which, as previouslyindicated, is a diode matrix including diodes 81 connected to the outputlines 8a of the binary to single output matrix 8. The latter matrix hasa separate output line for each character which can be displayed on thelamp bank and energization of one of these output lines 8a indicates thecharacter next to be fed to the right hand end of the lamp bank. The setlines 80-6, 80-5, 80-4, 80-3, 80-2, and 80-1 of the character readcontrol circuit 14 are respectively momentarily energized by a negativegoing voltage when the character read by the tape reader 7 isrespectively 1, 2, 3, 4, 5, and lamps wide when displayed on the lampbank 2. It is thus apparent that the various diodes 81 making up thecharacter with matrix associated with a given set input line 80 for thecharacter read control unit 14 are connected to all of the output lines8a of the binary to single output matrix 8 representing charactershaving the same width on the lamp bank.

Assuming, for example, that the character read by the tape reader 7 at agiven instant is to be 5 lamps wide, the set line 80-2 will be energizedat the instant tape reader 7 effects a read-out operation so as to setthe bistable circuit 77 associated with the second stage 14-2 of theshift register circuit 14. On the occurrence of the various A and Bpulses on the buses 33 and 33', the set state (constituting a shiftregister circuit marker) in the stage 14-2 will progress to the left, asviewed in FIG. 4.

As the memory bistable circuit 74 of shift register stage 14-8 istriggered into a set state, the positive going voltage appearing at theoutput 82 thereof is coupled through the capacitor 79 to a line 83 whichenergizes the binary to single output matrix 8 which, in turn, energizesthe character width matrix 15 and the character set-up matrix 10 stablecircuit 77 is coupled by an output line 86 to the shift input terminal7b of the tape reader 7 to move the next column 7a' of coded informationon the tape 7a into reading position in the tape reader. The output line86 is the character shift line 17 described in connection with FIG. 1.The movement of a set marker completely through the various stages ofthe shift register circuit making up the character read control circuit14 indicates that all of the set markers stored in the character memoryunit 6 have been transferred to the shift register circuits of the lampcontrol circuit 4.

LAMP CONTROL CIRCUIT 4b of FIG. 7

The lamp control circuit 4a of FIG. 3 will produce a complete lampenergizing pattern as, for example, illustrated for the letter E in FIG.6. As indicated in the introductory part of the Specification, letterslike the letter E have relatively long horizontal upper, lower andintermediate horizontal legs. The lamp rows Za, 2d and 2g of the lampbank which reproduce these legs of the letter E produce a much higheraverage intensity of illumination because of the successive energizationof these lamps as,

the letter E advances down the lamp bank than the lamp rows 2b, 2c, 2e,and 2g thereof. To minimize the Vdifference in the average intensity ofthe lamps in the various lamp rows and to reduce the number of stagesrequired in the shift register circuit forming part of the lamp controlcircuit 4, the lamp control circuit 4b of FIG. 7 was developed. Thiscircuit is similar in many respects to the circuit of FIG. 3 and similarportions thereof have been given similar reference numerals. The shiftregister circuit portion of the lamp control circuit 4b is identical tothat shown in FIG. 3 except that it requires only half the number ofstages. This is brought about by the fact that the lamp control bistablecircuits 28a-1, 28a-2, etc. are associated with alternate lamps 22a-1,22a-3, etc. of the lamp bank and the lamps 22a-2, 22a-4, etc. arecontrolled by the memory bistable units 30a-2, 30a-3, etc. The gated`diodes 20-2, 20-4, etc. associated with the lamps 22a-2, 22a-4, havecontrol terminals respectively connected to the output lines 41 of thememory bistable circuits 30a-2, 30a-3, etc. It is thus apparent thatwhen the memory bistable circuits 30a-2, 30a-3, etc. are in a set state,the resulting positive voltage occurring on the output lines 41 thereofwill re the associated gated diodes 20-2, 20-4, etc., which result inthe energization of the associated lamps for the remainder of the halfcycle involved. If the associated memory bistable circuits areimmediately reset by the B pulses as in the case of the lamp controlcircuit 4a of FIG. 3, the gated diodes will not be fired again until theassociated memory bistable circuits are again set, and so the lampscontrolled by the memory bistable circuits will not have sufficient timeto warm-up and remain lighted for a while at a readily visibleintensity. In other words, the length of time each of the memorybistable circuits 30a-2, 30a-3, etc. will be in the reset state dependsupon the time delay between each A pulse and the next B pulse. If the Aand B pulses occur during the same half cycle, the associated lamp willbe energized for only one-half cycle. Thus, when the lamp controlcircuit of FIG. 7 is used, the A and B pulses are preferably separatedby several half-cycles as illustrated by waveforms b and c in yFIG.7A sothe lamps will be energized for a number of half-cycles. As there shown,the A pulses are separated four half-cycles, the B pulses are separatedfour half-cycles, and the A and B pulses are spaced two half-cycles.This will result in the energization of the even numbered lamps 22a-2,22a-4, etc. for about three half-cycles since the memory bistablecircuit 30 are set for the interval between each A pulse and the next Bpulse. The odd numbered lamps 22a-1, 22a-3 will also be energized forabout three half-cycles due to the fact that the spacing between each Bpulse and the next A pulse determines the length of time the lampcontrol bistable circuits 28 remain set. The speed of the signprogression is actually the same for the A and B pulse timing shown inFIG. 7A used in the lamp control circuit of FIG. 7 and the A and Bpulses timing shown in FIG. 5, used in the lamp control circuit of FIG.5.

FIG. 8 illustrates those lamps which are energized at the instant of thesetting of the lamp control bistable circuits 28a-1, 28a-2, and 28a-3.When these lamp control bistable circuits become reset two half-cycleslater, the other lamps 28a-2, 22a-4 and 22a-6 to the left of the lampswhich were just energized become energized for three haflf-eycles. Thusfor a letter like the letter E, only half of the lamps in the row 2a, 2dand 2g forming the horizontal legs of the letter in lamp control circuitof FIG. 3 will be energized with the circuit of FIG. 7, thereby makingthe average intensity of the lamps in all the lamp rows of more equalintensity. Also, the circuit of FIG. 7 requires only one-half the shiftregister stages used in the circuit of FIG. 3.

MODIFIED LAMP CONTROL CIRCUIT FOR 4a' OF FIG. 9

Refer now to the lamp control circuit of FIG. 9 which is a modificationof the lamp control circuit shown in FIG. 3. As previously indicated,one of the problems in running signs is the problem of warm-up time forthe lamps. When a running sign is advanced along a lamp bank at a fairlyhigh running rate, it is frequently difcult to provide enough warm-uptime for the lamps. This problem is solved, in part, by the one cycleoverlapping energization of the lamps previously described in connectionwith the circuit of FIG. 3. FIG. 9 is an improvement over FIG. 3 byproviding a longer energizing period and greater degree of overlap ofthe energization fo the lamps without varying the phrasing or rate ofthe A and B pulses. In the preferred form of the invention, each of thelamp energizing bistable circuits 28a-1, 28a-2, etc. are bistablecircuits of special design including two current control devices (onlyone of which is shown in FIG. 9 and identified by reference number 90),wherein both devices are either in a non-conductive or a conductivestate, so that low drain operation can be effected when the lamp bank isnot energized. The current control device 90 illustrated is a PNPtransistor having an emitter electrode 91 connected by a conductor 92 toa positive direct current voltage bus 93, a collector electrode 96connected through a resistor 98 to ground and a base electrode 100,which is connected to a part of the bistable circuit to be describedlater on in connection with the circuit of FIG. 16. When a lamp controlbistable circuit 28 is in a set state, the current control device 90will be in a conductive state, resulting in a positive voltage at theungrounded end of the resistor 98. A conductor 102, couples theungrounded end of the resistor 98 to the anode side of an isolatingrectifier 104 whose anode is connected to the control terminal of theassociated gated diode 20. It is thus apparent that when any of thebistable circuits 28 are energized, a positive voltage is coupledthrough the rectifier 104 to effect yfiring of the associated gateddiode 20.

The improvement in the circuit of FIG. 9 over that of FIG. 3 is thateach bistable output conductor 102 is coupled to the anode side ofanother rectier 107 whose cathode is connected directly to the controlelectrode of the gated diode associated with the lamp which, in thenormal course of events, would be energized following the next shiftoperation of the shift register circuit controlling the row of lampsinvolved. The rectiiiers 104 Serve the purpose of isolating or blockingthe voltage fed to the control terminals of the gated diodes 20 throughthe rectifiers 107 from affecting the gated diodes associated with thenext stage of the shift register circuit. Thus, whenever a lamp controlbistable circuit 28 is in a set state, both the associated lamp and thelamp controlled by the next stage of the shift register circuit willalso be energized. Assuming that the set bistable circuit referred to isbistable circuit 28514, when it is reset during the next shiftoperation, the associated lamp 22a-1 will become de-energized at the endof the half-cycle involved, and the simultaneously lit lamp 22a-2associated with the next stage of the shift register circuit willcontinue to be energized due to the transfer of the set state of thelatter bistable circuit to the bistable circuit 28a-2 of the next stageof the shift register circuit. With this arrangement, each of the lampsto be energized is energized for a much greater period than the lamps inthe circuit of FIGS. 3 or 7, thereby giving a greater time for the lampsto warmup.

It should be noted that the transistors forming part of each of thebistable circuits 28 act as drivers for the gated diodes 20. The gateddiodes 20 and the bistable circuits 28 are most advantageously mountedupon or next to the `lamp bank 2. In such case, the positive voltage bus93 would be connected to a long conductor connecting these circuitcomponents to a remotely located source of positive direct currentvoltage. Spurious voltage can be picked up in this line which couldfalsely trigger the bistable circuits. The use of PNP transistors 90where the emitter electrodes 91 are connected by conductors 92 to thebus 93 extending to the source of direct current voltage feeding thisbus is an importnat feature of the circuit since the spurious voltagesignals coupled by the conductors 92 to the emitter electrodes 91 of thebistable circuit transistors 90 are isolated to a great extent from theother electrodes of the transistors associated with sensitive portionsof the bitable circuits relative to the case where NPN transistors areutilized for the transistors 90 requiring connections of their collectorelectrodes to the bus 93 which would then be connected to a groundedsource of negative voltage.

THE LAMP DIMMING CIRCUIT OF FIG. 10`

FIG. 10 illustrates a circuit which has for its purpose the selectivedimming of the upper, immediate and lower rows of lamps 2a, 2d and 2g inthe lamp bank more neanly to equalize the average intensity of all thelamps energized to display a letter like the letter E having extensiveupper, lower and intermediate horizontal legs. This circuit thusrepresents an improvement to the circuit of FIG. 7. The circuit of FIG.10 also adjusts the average intensity of the lamps in the lamp bank inaccordance with the ambient light conditions about the lamp bank. Inother words, as the ambient lamp conditions about the lamp bank varyduring weather conditions and the time of day, the average intensity ofthe light generated by the lights of the lamp bank will vary accordinglyso that the sign will appear with the same apparent sign brightness atall times and with use of minimum power.

The various rows of lamps 2a, 2b, 2c, 2d, 2e, 2f and 2g are respectivelyconnected to associated buses 24a, 24b, 24C, 24d, 24e, 24j and 24g. Thebuses 2419, 24C, 24e and 24f are connected directly to a branch line 109leading to a common conductor connected to the cathode terminal 112 of amain gated diode 114. The anode terminal 116 of the gated diode 114 isconnected to the output of the aforementioned full wave rectifiercircuit 60 (see F'IG. 3A) fed from a commercial 60 cycle per secondpower system. The upper, intermediate and lower buses 24a, 24d, and 24gare connected to the common conductor 110 through individual gateddiodes 119a, 119d, and 119g. The control terminals of the gated diodes119a, 119d and 119g are connected to a common conductor 121 leading tothe output of a suitable delay circuit 123. The input to the delaycircuit 123 is connected to the output of a variable phase pulse circuit125 which produces at its output pulses which vary in phase with thedegree of light striking a photocell 127, which is positioned to respondto the ambient light conditions of the lamp bank. The input to thevariable phase pulse generator circuit 125 is connected to the output ofthe aforementioned full wave rectifier circuit 60 so that the outputthereof contains pulses at a rate of 120 pulses per second. The outputof the variable phase pulse circuit 125 is connected by a conductor 128to the control electrode 129 of the gated diode 114. The gated diode 114will thus fire each half-cycle at a phase angle which is a function ofthe ambient light condition striking photocell 127 and will remain inthe conductive state for the remainder of the half-cycle involved.Accordingly, the pulse width of the current flowing through the gateddiode 114 is inversely proportional to the intensity of the lightstriking the photocell 127.

The phase angle of the pulses fed to the control electrodes of the gateddiodes 119a, 119d and 119g, associated with the upper, intermediate andlower rows of lamps 2a, 2d and 2g in the lamp bank is delayed somewhat(such as 30 degrees) from the phase angle of the pulses which triggerthe main gated diode 114, so that the width of the current pulsesflowing through the gated diodes 11911, 119d and 119g will be less thanthe current pulsations received by the lamps in the lamp rows 2b, 2c, 2eand 2f. Thus the apparent intensity of the light generated by the lampsof all the rows of the lamp bank in the circuit arrangement of FIG. lwill be fairly constant despite variations in ambient light conditionsand despite the fact that the lamps in the uppermost intermediate andlower rows of the lamps in the lamp bank will be energized in timesuccession more frequently than the lamps of the other rows of lamps.

THE VARIABLE PHASE PULSE CIRCUIT 125 OF FIG. 12

FIG. l2 illustrates an exemplary variable phase pulse circuit which ismost advantageously used for the circuit 125 shown in box form in FIG.10. This circuit may include a clipper circuit 62 for clipping the fullwave rectified waveform fed thereto from the full wave rectifier 60, adifferentiating network 64 for differentiating the waveform at theoutput of the clipper circuit, and a rectifier 66' for passing pulses ofonly one polarity, such as positive pulses occurring at a rate of 120pulses per second. It is apparent that the circuits `62 and 64 and therectifier 66 may be the same corresponding by numbered elements as shownin FIG. 3A which form part of the shift pulse generator circuit 13.

The 120 pulse per second output of the rectifier 66 is fed to the setinput S of a conventional bistable circuit 130. The bistable circuit 130illustrated has an output line 132 connected to a rectifier 134 arrangedto pass a negative or ground voltage and to block a positive voltage.When the bistable circuit 130 is set, the upper line 132 has a positivevoltage and when it is reset iu a manner to be explained the voltage atthe output line 132 is at ground potential.

The anode side of the rectifier 134 is connected to the ungrounded endof a grounded capacitor 136. The unground end of the capacitor 136 isconnected to the emitter electrode 136 of a double base diode 138 havingone of its bases 140 connected to a positive bus 141 extending to thepositive terminal of a source of positive direct current voltage andanother base 143 connected through a resistor 145 to the ground. Theaforementioned photocell 127 is connected between the emitter electrode136 and a resistor 144 connected to the positive bus 141. It should bethus apparent that when the bistable circuit 130 is in a set statewherein the rectifier 13 4 blocks the resulting positive voltage on theoutput line 132, the double base diode 138 andthe associated elementsincluding the capacitor 136, photocell 127 and resistor 144 form arelaxation oscillator circuit of wellknown design (except for thephotocell) where the voltage across the capacitor 136 rises at a ratedepending upon the intensity of the light striking the photocell 127. Asa greater amount of light strikes the photocell 127, the impedancethereof decreases to increase the charging vrate of the capacitor 13S.The voltage across the capacitor 136 will, therefore, reach the voltagewhich causes firing of the double base diode much sooner when the lightstriking the photocell 127 is at a high intensity than when it is at alower intensity. When the double base diode 138 fires, a voltage pulsewill appear across resistor 145 as the capacitor 136 discharges. Thispulse is fed through a resistor 147 to the control terminal of the maingated diode 114 controlling the ow of current to the buses of the lampsin the lamp bank.

The pulse appearing across the resistor is also coupled by a conductorto the reset input R of the bistable circuit 130 to reset the same. Whenthe bistable circuit 130y is reset, as previously indicated, the voltageon the output line 132 thereof becomes grounded. This ground potentialis passed by the rectifier 134 to the ungrounded end of the capacitor136, which: is thereby maintained in a discharged state until the nextpulse from the rectifier 66 is fed to the set input S of the bistablecircuit 130. It is thus apparent that the ungrounded end of the resistor145 has produced thereat pulses at a repetition rate of 120 cycles persecond and at a phase angle depending upon the intensity of the lightstriking the photocell 127.

SHIFT REGISTER CIRCUIT OF FIG. 13

In the exemplary forms of the invention described above, the shiftregister circuits included intermediate or memory bistable circuits 30which carry out the function of the condition sensing means shown in-box form in the generalized disclosure of the invention of FIG. 1.Although less preferred, each memory bistable circuit 30 can be replacedby a NORAND gate circuit generally indicated by reference numeral 30 inFIG. 13. Each of the circuits 30 has input terminals 152 and 153 andoutput terminals 154 and 155. Input terminal 153 extends directly to theoutput line 41 of a bistable circuit 28 which may control theenergization of one of the lamps of the lamp bank. The other inputterminal 152 extends to the B pulse bus 33.

Assuming that the B bus pulses are positive pulses, each circuit 30would feed a setting signal to the set terminal S of the bistablecircuit 28 of the associated stage of the shift register circuit if thevoltages on the input treminals 153 and 152 are both positive. (It willbe recalled that, in the shaft register circuits used particularly forthe lamp control circuit, the voltage on the output lines 41 arepositive during the set state of the associated bistable circuits.) Thisresult can be accomplished by a well known simple AND logic circuit. If,on the other hand, the voltage on input terminal 153 is ground ornegative while the voltage on the other input terminal 152 is positive(or vice versa), a reset signal will be generated at the output terminal155 which is coupled by a conductor 158 to the reset terminal R of thebistable circuit 28. A NOR logic circuit will accomplish this function.

It can Ibe seen that with the circuit arrangement just described, thearrangement of bistable circuits and the NOR-AND circuits just describedthat a shift register circuit is provided which carries out the samefunctions as the shift register circuit shown in FIGS. 3, 4 and 9(although it could not perform the function of the circuit of FIG. 7).

COMBINED RUNNING AND STATIONARY SIGN SYSTEM OF FIG. 14

The circuit of FIG. 14 has many of the components present in thesimplified embodiment of the invention shown in FIG. 1 and in thedimming control circuit of FIGS. 10 and 12 and the same referencecharacters have been used therein to indicate corresponding elements.

The circuits previously described deal with a system for producing arunning sign on a lamp bank. The circuit of FIG. 14 accomplishes thisresult and, in addition, provides for stopping a running sign at a givenpoint as determined by the presence of a stop code appearing in a columnof the tape 7a read by the tape reader 7. This stop code may be anysuitable code which differs from the binary code groups identifying thealphabet and numerical characters displayed on the lamp bank. A seriesof conductors 162 extend respectively from the various output lines 7cof the tape reader 7 to the input of a decoding matrix 160 havingseparate output lines 164-1, 164-2 164-6 representing stop codes forstopping the sign respectively for 6 different intervals (such as 5, 10,15, 20, and 30 seconds). Obviously a greater number of stop codes couldbe provided for giving a larger variety of stopping periods. The decoder160 is a conventional diode-type matrix which will energize the outputline 164 which is associated with the time period identified by thebinary code read by the tape reader 7 representing one of the stop codesreferred to. It will be assumed that, when the output lines 164-1, 164-2164-6 are respectively energized, this represents respectively sixprogressively increasing time periods during which the sign thendisplayed on the lamp bank will be stopped on the lamp bank.

The various decoder output lines 164 are respectively connected to an ORcircuit which is a Well-known circuit which will produce a signal at theoutput terminal 166 thereof when a given signal appears on any one ofthe inputs thereto. It is thus apparent that the OR circuit 166 willprovide an output signal if a stop code is sensed by the tape reader 7.When such a signal occurs, it is fed by conductor 168 to the set inputterminal S of a control bistable circuit 168, to effect setting of thebistable circuit upon the presence of any stop code.

A subtract shift register 170I of any one of a number of differentdesigns may be provided. For example, it may be a shift register with anumber of stages corresponding to the number of different basic timeperiods. In such case, the various output lines 164 of the decoder 160may extend respectively to the set terminals S of the various stages ofthis shift register to set a marker in the stage of the shift registercorresponding to the time period involved. Asource 172 of shift pulsesfor the shift register 170 is provided where the shift pulses may beseparated, for example, five seconds apart. It is thus apparent that ifthere is a marker stored in the No. 6 stage of the shift register 170,the marker will be read out of the first stage of the shift registercircuit approximately thirty seconds after the marker was initiallyplaced into the shift register. When the marker is shifted out of theNo. 1 stage of the shift register circuit, a voltage appears in anoutput line 174 which is fed to the reset input terminal R of thecontrol bistable circuit 168 to reset the same.

The control bistable circuit 168 has a pair of output lines 171 and 173which, during the set state of the bistable circuit, may, for example,respectively have a positive voltage and ground thereon and during thereset state of the bistable circuit respectively have ground and apositive voltage thereon. The output line 171 extends to the input ofthe pair of gate circuits 174 and 176. The presence of a positivevoltage on the line 171 results in the closing of the gate circuits 174and 176 and the presence of a ground voltage thereon will result in theopening of the gate circuits.

The gate circuit 174 has input lines 180` extending from the A and Boutputs of the shift pulse generator circuit 13 and output lines 182extending to the A and B buses of the character read control circuit 14,the lamp control circuit 4 and the character memory unit 6. The gatecircuit 176 has a pair of input terminals 183-183 respectively connectedto the advance and read lines 86 and 83 of the character read controlcircuit 14 and output lines 18S-185 extending respectively to theadvance and read terminals of the tape reader 7 and the matrix 8.

It is thus apparent that when a stop code is being read by the tapereader 7, a set signal will appear on an output of the OR circuit 166which will effect the setting of the control bistable circuit 168 which,in turn, results in the closing of the gate circuits 174 and 176 to stopthe advancement of markers within the various shift register circuits ofthe lamp control circuit 4, the character memory unit 6 and thecharacter read control circuit 14, and the stopping of the sign on thelamp bank 2 for a period determined by the duration the control bistablecircuit 168 remains in a set state. As previously indicated, the controlbistable unit 168 will be reset when the marker in the substractregister is removed from the No. l stage of the register.

The particular circuit disclosed in FIG. 14 is one Wherein the apparentintensity of the lamp bank 4 remains constant with variation of theambient light conditions about the lamp bank 2 and also with the natureof the sign on the lamp bank. When a running sign is stopped, theintensity of the light generator by the lamps is increased if thecurrent flow through the lamps is not altered. In other words, when thesign on the lamp bank is stationary, the amount of current flow throughthe lamps thereof to produce a given light intensity is less than thecurrent required by the lamps to produce the same light intensity in arunning sign. The circuit of FIG. 14 reduces the width of the currentpulses fed to the lamps when a stationary sign is displayed on the lampbank. To this end, the time constant of the capacitor charge circuit ofthe double base diode relaxation oscillator circuit controlling thefiring time of the main gated diode 114 is varied with the ambient lightconditions of the lamp bank as well as the nature of the sign on thelamp bank 4.

The charge circuit for the capacitor 136 connected between the emitterelectrode of the double base diode 138 and ground includes, in 'additionto the photocell 127, a pair of branch circuits extending respectivelyto the output lines 168 and 171 of the control bistable circuit 168. Oneof the branch circuits includes an adjusting resistor 144 and arectifier 186 extending to the output line 173 of the control bistableunit 168 which is positive during the reset state of the bistablecircuit and ground during the set state of the bistable circuit. Therectifier 186 is arranged to pass a positive voltage on the output line173 and block ground from the charge circuit of capacitor 136.Accordingly, when a running sign is displayed on the lamp bank, the timeconstant of the circuit which charges the capacitor 136 is determined bythe value of the adjusting resistor 144.

The other branch circuit in the charge circuit of the capacitor 136includes an adjusting resistor 144 and a rectifier 186' connected to theother output line 171 of the control bistable circuit which is at groundduring the reset state of the bistable circuit and positive during theset state of the bistable circuit. The rectier 186' blocks ground fromand passes positive Voltage to the charge circuit. Accordingly, when astationary sign is displayed on the lamp bank, the time constant of thecircuit which charges the capacitor 176 is determined by the value ofresistor 144 which is larger than the resistor 144, to delay the tiringtime of the main gated diode 114.

EX-EMPLARY BINARY TO SINGLE OUTPUT MATRIX 8 OF FIG. l5

FIG. 15 shows an exemplary circuit for the binary to single outputmatrix 8 and the input and output devices and circuitry associatedtherewith. One of the input devices is the tape reader 7, which may beany one of a number of conventional tape readers. As illustrated thetape reader 7 has a set of six contacts 7d, each of which includes aspring urged movable contact 7d-1 which is adapted to pass through ahole of the tape 7a and a stationary contact 7d-2 which is engaged bythe movable contact when the latter contact passes through the hole inthe tape.

IEach of the stationary contacts 7d-2 is connected to a common conductor201 which is grounded. The movable contacts 7d-1 are respectivelyconnected to separate buses 204. The buses 204 are connected throughrespective resistors 206 to a common conductor 207 leading to thepositive terminal of a source of direct current voltage 208 whosenegative terminal is grounded. It is thus apparent that when a movablecontact 7d-1 of the tape reader 7 passes through a hole in tape 7a toengage the associated stationary contacts 7d-2 the associated bus 204will be grounded and when the latter contacts are separated theassociated bus 204 will be at a positive potential.

IEach of the buses 204 are connected through a separate resistor 211 anda resistor 209 to the negative terminal of a source of negative voltage(not shown) whose positive terminal is grounded. The juncture betweeneach associated pair of resistors 207 and 209 is connected by aconductor 210 to the base electrode 212b of an NPN transistor 212. Theemitter electrode 212a of each transistor is grounded and the collectorelectrode 212C thereof is connected through a resistor 214 to theaforementioned bus 207 leading the positive terminal of the source ofdirect current voltage 208. The transistors 212 and associated circuitsform part of the matrix 8. It is apparent that when a bus 204 isgrounded the base electrode 212b of the associated transistor 212 willhave a negative potential thereon which will render the NPN transistor212 involved non-conductive. The ratio of the resistors 207 and 209 issuch that when the associated bus 204 has a positive potential, theconductor 210 extending from the juncture of these resistors will be ata positive potential so as to render the associated transistors 212conductive.

A conductor 220 extends from the end of each resistor 214 adjacent tothe collector electrode 212e of the associated transistor 212 and aseparate code bus 217. The various code buses 217 are identifiedrespectively by references numerals 217a, 217b, 217e and 217d, 217e and217i. When a transistor 212 is conducting, the associated conductor 220and bus 217 will be at ground potential and when the transistor isnon-conductive the conductor 220 and associated bus 217 will be at apositive potential. The various code buses 217 are connected throughrespective rectiliers 219 to ground, the rectiiiers being arranged toblock positive voltage and pass ground or a negative voltage.

A gating bus 220 is provided which is connected through a resistor 221to the positive bus 207. The gating bus 220 is connected to thecollector electrode 224C of an NPN transistor 224. The emitter electrode224a of the transistor 224 is grounded and the base electrode 224bthereof is connected through a resistor 226 to the negative terminal ofthe source of negative voltage 227 whose positive terminal is grounded,and through a resistor l228 to a coupling capacitor 230 connected to theline 83 extending from the character read control circuit 14. A positivepulse will appear on the line 83 when a marker is being removed from thelast stage of the shift register circuit constituting the character readcontrol circuit 14. Ground clamping diodes 231 and 232 are respectivelyconnected between the input side of the resistor 228 and the collectorelectrode 224e of transistor 224 and ground. These rectiers bypass anynegative voltage which may appear in the inputs to these rectiers fromthe circuits coupled thereto.

When a positive pulse appears on the line 83 extending from thecharacter read control circuit 14, this will render the transistor 224conductive to couple ground potential to the gating bus 220. Normally,the gating bus 220 is positive due to the normal non-conductive state oftransistor 224. The transistor 224 is rendered non-conductive by theconnection of the base electrode 224b thereof through the resistor `226to the negative terminal of the source of direct current voltage 227.

The potentials on the various code buses 217 and the gating bus 219control the operation of AND circuits 240-1, `240-2, 240-3, 240-4, etc.,there being one such AND circuit for each character to be displayed onthe bank lamp. `Each of the AND circuits 240 includes an NPN transistor242 having an emitter electrode 242a which is grounded, a base electrode242b which is coupled by ya conductor 243 to one of the ends of a groupof seven resistors 244-1, 244-2 244-7, and a collector electrode 242Cconnected through a resistor 241 to the positive bus 207. Each of theresistors 244 is assigned to one of the seven buses 220, 217a, 217b,217C, 217e and 2171.4 The resistors 244-7 are all permanently connectedto the gating bus. The other resistors of the group associated with eachAND circuit are connected in different patterns to the various codebuses 217:1-217) so that the group of resistor associated with a givenAND circuit will all be connected to ground bus only for the particularcharacter involved. At all other times, at least all the other resistors244-1 through 244-6 will be connected to a bus which is positive.

The conductor 243 associated with each of the AND circuits is alsoconnected to one end of a resistor 248 whose opposite end is connectedto the negative terminals of a source of direct current voltage (notshown) whose positive terminal is grounded.

The ratio of the resistors 248 to the resistors 244 is such that, whenone of the resistors 244-1 through 244-7 of a group is connected to apositive "bus, the potential on the conductor 243 leading to the baseelectrode 2421; of the associated transistor 242 will be positive torender the same conductive and, when all of the resistors 244-1 through244-7 of a group are connected to grounded buses, which occurs onlymomentarily when a gating pulse appears on the bus 220, the potential ofthe asso- Ciated conductor 243 will be negative to render the associatedtransistor 242 non-conductive. Thus, a different one of the transistors242 will be rendered non-conductive upon the appearance of a gating orread pulse on the input line 83 for a different character read by thetape reader 7. As a transistor 242 becomes momentarily nonconductive, apositive going voltage will appear at the end of the associated resistor241, connected to the collector electrode 242C thereof. This voltage iscoupled through a capacitor 250 to a group of diodes 11 forming part ofthe character set-up matrix 10. As previously indicated, the dodes 11associated with a particular output of the matrix 10 are connected toset various bistable circuits of the character memory unit 6.

EXEMPLARY SHIFT REGISTER BISTABLE CIRCUIT OF FIG. 16

The bistable circuit of the lamp control circuit 4 which control thegated diodes 20 draw a relatively large amount of current and it is,therefore, desirable that the current drain of the bistable circuits berelatively low when the lamps controlled thereby are in a de-energizedstate. To this end, each of the bistable circuits 28 and 30 of the shiftregister circuits constituting the lamp control circuit 4 comprises apair of transistors 90 and 90 which are respectively in a highlyconductive state during the set state of the bistable circuit and areboth in a non-conductive state during the reset state of the bistablecircuit. One of the transistors 90 is a PNP transistor, and thetransistor is an NPN transistor. (Since the circuitry for each bistablecircuit is identical, only the circuit 28a-1 of. one of them will bedescribed in detail.)

The collector electrode 91 of the transistor 90 is connected byconductor 92 to a positive bus 93 leading to the positive terminal ofthe source of positive voltage (not shown) whose negative terminal isgrounded. (The bus 93, for example, may be a at volta-ge of 18 volts.)The collector electrode 96 of the transistor 90 is connected through aresistor 98 to ground.

The transistor 90 has an emitter electrode 260 which is connected to thereset terminal R. The reset terminal R is connected by a conductor 262to the A bus 33. The collector electrode 264 of the transistor 90 isconnected by a resistor 266 to a positive bus 93', which may have apositive voltage of 22 volts. The collector electrode 264 of thetransistor 90 is also connected through a resistor 270 to the baseelectrode 100 of the transistor 90. The set terminal S of the bistablecircuit is connected to the base electrode 100 of the transistor 90. Aresistor 272 is connected between the base electrode 274 of thetransistor 90' and the ungrounded side of the resistor 98.

One of the advantages of the circuit shown in FIG. 16 is that thebistable circuits can be triggered from a reset state into a set stateby the simple expedient of opening lines extending to the A and B buses33 and 33. This minimizes pulse distortion problems and the like whichoften occur when voltage control pulses are sent down long lines. (Thevarious voltage sources which operate the bistable circuits shown inFIG. 16 are normally located a great distance from the lamp bank atwhich the bistable circuits are located.) To this end, the circuit shownin FIG. 3A is modied so that the pulses appearing at the A and B outputterminals of the shift pulse generator circuit will be negative ratherthan positive pulses. The A and B output terminals of the shift pulsegenerator circuit are respectively connected `to the base electrodes 280and 280 of a pair of NPN control transistors 282 and 282. The collectorelectrodes 283 and 283 of these transistors `are respectively connectedthrough resistors 286 and 286 to the aforementioned positive bus 93. Theemitter electrodes 287-287 of these transistors are coupled throughdiodes 289-289 to ground, the diodes being arranged to pass normalcollector to emitter current. The base electrodes 280 and 280 of thesetransistors are coupled through resistors 290 and 290' to the positiveterminal of a source of direct current voltage o (not shown) whichopposite terminal is grounded. The collector elcetrodes 283 and 283 ofthe transistors 282 and 282 are connected by conductors 291 and 291respectively to the A and B buses 33 and 33.

Normally, the control transistors 282 and 282 are in a conductive statedue to the feeding of a positive voltage through the resistors 290 and290 to the base electrodes 280 and 280 of the transistors 282 and 282.Conduction of these transistors couples ground potential to the buses 33and 33.

The various bistable circuits 28 and 30 illustrated in FIG. 16 arenormally in their reset state where the transistors 90 and 90" arenon-conductive. These transistors are maintained in a nonconductivestate by virtue of the connection of the positive voltage on the bus 93through the resistors 266 and 270 to the base electrodes 100 of thetransistors 90. As long as transistors 90` are non-conductive, groundpotential is coupled through the associated resistors 282 to the baseelectrodes 274 of the associated transistors 90 which, since they areNPN transistors, render them non-conductive. The bistable circuit istriggered into a set state by the feeding of a negative pulse to the setterminal S thereof connected to the `base electrode 100 of theassociated NPN transistor 90. This renders the transistor 90 conductivewhich results in the voltage at the top of the associated resistor 98being positive. This positive voltage is coupled through the resistor272 to the base electrode 274 of the associated NPN transistor 90 torender the same conductive. When the transistor 90' becomes conductive,ground potential is coupled through the resistor 270, the base electrode100, to the transistor 90 to maintain the same in a conductive state.

Each bistable circuit is reset by the simple expedient of momentarilyopening the lines 291 and 291 leading to the buses 33 or 33. Thisinterrupts flow of current to the transistor 90. As the transistor 90 isrendered nonconductive in this manner, the aforementioned groundpotential fed through the resistor 270 to the base electrode 100 of thetransistor 90 is removed and replaced by a positive voltage fed from thebus 93 which renders the transistor 90 non-conductive. therebyreestablishing a stable nonconductive state for both transistors 90 and90.

The ground potential is removed from the buses 33 28 and 33' by thepresence of a negative pulse on the A and B terminals leading to thebase electrodes 280 and 280 of the control transistors 282 and 282'.This negative pulse will momentarily render the NPN transistors 282 and282 non-conductive, thereby disconnecting ground potential from thebuses 33 and 33'.

It should be understood that many modifications may be made in thevarious preferred forms of the invention described above withoutdeviating from the broader aspects of the invention. For example,although the embodiment of FIG. 14 is applied to a combination runningand stationary sign, many of the features therein are applicable to anon-running stationary sign system wherein the energization of the lampsis blocked out until the movement of the markers in the various shiftregisters is terminated.

We claim:

1. In combination with a running sign system including a source ofenergizing voltage, a lamp bank containing an upper and lower row oflamp banks which are energized to form horizontal upper and lower legsof various letters of the alphabet and intermediate rows of lamp banksbetween said upper and lower rows of lamps, one of which rows has lampsto be energized to form the horizontal central legs of various lettersof the alphabet, and control means for energizing the lamps in thevarious rows in accordance with a pattern which proceeds horizontallyacross the lamp bank, said control means including switch means forcompleting circuits between said source of energizing voltage and thelamps in the bank in accordance with a predetermined sign formingprogram, the circuits for the lamps in said upper, lower and said oneintermediate row of lamps including average current reducing means forproducing a lower average current in the associated rows of lamp banksduring the completion of .the circuits than in the other intermediaterows of lamps to equalize the average intensity of the light produced bythe lamp forming the horizontal upper and lower and central legs of theletters of the alphabet which are successively energized at a higherrate with the intensity of the light produced by said other intermediaterows of lamps as one of said letters proceeds across the sign.

2. The combination of claim 1 wherein there is provided between saidsource of energizing voltage and all of said lamps a common averagecurrent varying means for progressively varying simultaneously theaverage current flow through the lamps, light sensing means for sensingthe ambient light conditions of the lamp bank, and means responsive tosaid light sensing means for operating said average current varyingmeans to make the average current in said lamps inversely proportionalto the ambient light conditions of the lamp bank.

3. In a combined running and stationary sign system including a lampbank, a source of current for energizing the lamp bank and input meansfor receiving sign information to be displayed on the lamp bank and stoporder information constituting an order to stop the running sign, theimprovement comprising control means responsive to the information fedto said input means for completing lamp energizing circuits between saidsource of current and the lamps in the lamp bank for normally effectingthe movement of sign information across said lamp bank and to stop themovement of the running sign when said stop order information isreceived, dimming means for eifecting a relatively low level of averagecurrent flow in said lamp energizing circuits when in a rst state foreffecting a relatively high level of average current flow in said lampenergizing circuits when in a second state, and means responsive to saidstop order information for automatically operating said dimming means insaid irst low current state when the sign information on said bank isstationary and responsive to the absence of said stop order informationfor automatically operating said dimming means in said second state 22when the sign information on said lamp bank is moving, 3,084,338 4/ 1963Maner et a1. 340-213 wherein the intensity of the light from said lampsis 3,166,742 1/ 1965 Sherwin 340-334 more nearly equal for running andstationary signs on 3,384,888 5/ 1968 Hamden et al. 340-339 the lampbank. 3,389,389 6/ 1968 Minear 340-339 References Cited 5 DONALD J.YUSKO, Primary Examiner UNITED STATES PATENTS DAVID L. TRAFTON,Assistant Examiner 1,946,297 2/ 1934 Suits 340-334UX 1,974,318 9/1934suits 34a-334x U-S- Cl- X-R 2,123,459 7/1938 Andersen 340-334X l0340-332, 339

